Regviz

Silicon Labs /Series1 /MGM13 /MGM13P12F512GA /USART0 /CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/Series1/MGM13/MGM13P12F512GA/USART2/CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SYNC)SYNC 0 (LOOPBK)LOOPBK 0 (CCEN)CCEN 0 (MPM)MPM 0 (MPAB)MPAB 0 (X16)OVS0 (CLKPOL)CLKPOL 0 (CLKPHA)CLKPHA 0 (MSBF)MSBF 0 (CSMA)CSMA 0 (TXBIL)TXBIL 0 (RXINV)RXINV 0 (TXINV)TXINV 0 (CSINV)CSINV 0 (AUTOCS)AUTOCS 0 (AUTOTRI)AUTOTRI 0 (SCMODE)SCMODE 0 (SCRETRANS)SCRETRANS 0 (SKIPPERRF)SKIPPERRF 0 (BIT8DV)BIT8DV 0 (ERRSDMA)ERRSDMA 0 (ERRSRX)ERRSRX 0 (ERRSTX)ERRSTX 0 (SSSEARLY)SSSEARLY 0 (BYTESWAP)BYTESWAP 0 (AUTOTX)AUTOTX 0 (MVDIS)MVDIS 0 (SMSDELAY)SMSDELAY

OVS=X16

Description

Control Register

Fields

SYNC

USART Synchronous Mode
LOOPBK

Loopback Enable
CCEN

Collision Check Enable
MPM

Multi-Processor Mode
MPAB

Multi-Processor Address-Bit
OVS

Oversampling

0 (X16): Regular UART mode with 16X oversampling in asynchronous mode

1 (X8): Double speed with 8X oversampling in asynchronous mode

2 (X6): 6X oversampling in asynchronous mode

3 (X4): Quadruple speed with 4X oversampling in asynchronous mode
CLKPOL

Clock Polarity
CLKPHA

Clock Edge for Setup/Sample
MSBF

Most Significant Bit First
CSMA

Action on Slave-Select in Master Mode
TXBIL

TX Buffer Interrupt Level
RXINV

Receiver Input Invert
TXINV

Transmitter Output Invert
CSINV

Chip Select Invert
AUTOCS

Automatic Chip Select
AUTOTRI

Automatic TX Tristate
SCMODE

SmartCard Mode
SCRETRANS

SmartCard Retransmit
SKIPPERRF

Skip Parity Error Frames
BIT8DV

Bit 8 Default Value
ERRSDMA

Halt DMA on Error
ERRSRX

Disable RX on Error
ERRSTX

Disable TX on Error
SSSEARLY

Synchronous Slave Setup Early
BYTESWAP

Byteswap in Double Accesses
AUTOTX

Always Transmit When RX Not Full
MVDIS

Majority Vote Disable
SMSDELAY

Synchronous Master Sample Delay

Links

()

Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data